Along with advancements in miniaturization, faster operation, and a higher degree of integration of semiconductor devices, electrode pads that are provided on a substrate, where the semiconductor devices are formed in order to electrically connect the semiconductor devices to an exterior circuit, can be further reduced in size.
Incidentally, there is a highly integrated semiconductor device formed by stacking plural substrates having miniaturized, high speed, and highly integrated semiconductor elements therein.
In such a semiconductor device composed of plural substrates where the semiconductor elements are formed, the stacking structure must be formed after the electrode pads of the substrates to be stacked are aligned with a high degree of accuracy in order to assure electrically connecting the electrode pads, even when the electrode pads are further reduced in size. There have been disclosed several manufacturing methods of manufacturing the semiconductor device, which includes a method of aligning the substrates and a method of forming the stacking structure.
For example, Patent Document 1 discloses a method of applying an adhesive between the substrates, optically detecting patterns formed in the substrates, tentatively aligning the substrates, verifying positions of the substrate by X-ray fluoroscopy, adjusting the positions of the substrate in accordance with information regarding the positions, and then applying and hardening the adhesive.
In addition, Patent Document 2 discloses a method employing a substrate holding surface of the substrate holder, the surface being divided into plural holding areas, which are capable of independently controlling a suction force that attracts the substrate and/or a pressing force that presses one of the substrates onto the other in each of the holding areas.    Patent Document 1: Japanese Patent Application Laid-Open Publication No. 2009-49051.    Patent Document 2: Japanese Patent Application Laid-Open Publication No. 2005-302858.